A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having crossing cubic wirings and its manufacture method.
B) Description of the Related Art
As an integration degree of semiconductor devices is improved, wirings are becoming finer. An integration degree of lower layer wirings near a semiconductor substrate is particularly high and there is high demands for miniaturization. Even if wirings are made fine, it is desired to lower parasitic resistance and parasitic capacitance. Various proposals have been made for lowering parasitic resistance and capacitance.
A conductive plug is formed by forming an insulating film on an underlying layer having a conductive layer, forming a contact hole for the conductive layer, embedding polysilicon or tungsten in the contact hole by chemical vapor deposition and removing an unnecessary portion by etch-back or chemical mechanical polishing (CMP).
After the connection region is led upward by the conductive plug, a damascene wiring is used often. The damascene wiring is formed by forming an insulating film, forming an interlayer connection via hole and a wiring trench in the insulating film, embedding a conductive layer in the via hole and wiring trench and removing an unnecessary portion by CMP or etch-back. For example, after the via hole and wiring trench are formed, a barrier layer of TiN, TaN or the like and a copper layer are formed by sputtering, and a copper layer is formed by electroplating. This method is suitable for forming a wiring having a high precision by using copper with a low resistivity.
There are high demands for improving an integration degree of a semiconductor device having a repetitive pattern such as memories. Various proposals have been made for improving wiring patterns. It is necessary to form in addition to a control gate, a ground source wiring and a read drain wiring (bit line) for a flash memory. Crossed wirings are therefore necessary.
JP-A-2001-244353 proposes to form a wall-like conductive plug extending along a word line direction for a source diffusion layer of a flash memory element, and form an isolated column-like conductive plug for the drain diffusion layer.
FIGS. 11A, 11B, 11C and 11D show a typical wiring structure disclosed in JP-A-2002-244353. FIG. 11A is a plan view. FIGS. 11B, 11C and 11D are cross sectional views taken along lines III-III, IV-IV and V-V, respectively.
Referring to FIG. 11A, a first source line SL1 is a wall-like conductive plug connected to a source diffusion layer of a memory device, disposed vertically in FIG. 11A and being parallel to a word line. A drain contact plug DCP is an isolated column-like conductive plug formed on each drain diffusion layer of the memory device. A drain line DL is a drain wiring disposed horizontally in FIG. 11A and connected to the drain contact plug DCP. An insulating layer is involved between the drain line DL and first source line SL1. A second source line SL2 and the drain line DL are alternately disposed horizontally.
As shown in FIG. 11B, the drain contact plug DCP is a column-like plug made of a first drain contact plug DCP1 buried in a first interlayer insulating film IL1 and a second drain contact plug DCP2 buried in a second interlayer insulating film IL2 and stacked on the first drain contact plug DCP1. The drain line DL is formed by growing a conductive film of Al or the like on the second interlayer insulating film IL2 and pattering the film.
Stacked on a semiconductor substrate 130 are a tunnel insulating film 132, a floating gate 133, an insulating film 134, a word line (control gate) WL and a protective oxide film 136, and on this lamination structure, a silicon nitride film 137 and the first interlayer insulation film IL1 are formed. In the following, the first interlayer insulating film IL1 and silicon nitride film 137 are collectively called the first interlayer insulating film IL1.
As shown in FIGS. 11B and 11C, the first source line SL1 is buried in the first interlayer insulating film IL1 and extends parallel to the word line WL. A ground line resistance is lowered by forming the wall-like conductive plug having the same height as that of the first interlayer insulating film IL1.
As shown in FIG. 11D, the second source line SL2 has the structure similar to the drain line DL and extends parallel to the drain line. A source contact plug SCP is formed in the second interlayer insulating film at the position where the first source line SL1 and second source line SL2 cross, to electrically connect the first and second source lines.
The first drain contact plug DCP1 and first source line SL1 are formed in a self-alignment manner relative to the word line WL to improve an integration degree. However, as shown in FIG. 11D, the second drain contact plug cannot be formed under the second source line SL2 so that the memory elements under the second source line SL2 are dummy. This publication does not teach mixture of a memory circuit and a peripheral circuit.
Similar structures to the structure of the above-described conductive plug are also disclosed in JP-A-HEI-7-74326, JP-2001-111013 and JP-A-2001-203286.
Patent Document 1
JP-A-2001-244353
Patent Document 2
JP-A-HEI-7-74326
Patent Document 3
JP-A-2001-111013
Patent Document 4
JP-A-2001-203286
If a memory circuit and a peripheral logic circuit are mixedly mounted, wirings of the memory circuit are required to have a low parasitic capacitance, and wirings of the peripheral logic circuit are required to have a low parasitic resistance. These requirements are hard to be met by using the same wiring structure. In order to meet these requirements, it is effective that thin wirings are formed in the memory circuit and thick wirings are formed in the peripheral circuit.
Thin wirings in the memory circuit and thick wirings in the peripheral logic circuit can be formed by etching and lowering a lower interlayer insulating film in the peripheral circuit, forming an etch stopper layer and an upper interlayer insulating film and forming damascene wirings.
Patent Document 5
JP-A-HEI-10-223858
Patent Document 6
JP-A-HEI-10-200075
Thick and thin wirings can also be formed by performing wiring trench forming etching twice by using different masks to form deep and shallow trenches, and embedding wirings in the trenches.
Patent Document 7
JP-A-HEI-11-307742
Patent Document 8
JP-A-HEI-9-321046
Patent Document 9
JP-A-2000-77407